1. Field of the Invention
The present invention relates to an LSI tester and more particularly to an LSI tester for use in analyzing a possible defect, fault or the like of an LSI(large-scale integrated circuit).
2. Description of the Related Art
In analyzing a possible fault of LSI, particularly in specifying the fault position in the LSI, it has been a common practice to carry out a fault simulation on a computer or to use an EB (electron beam) tester.
Attempts have been made to locate the fault position more precisely in a simpler manner. For example, Japanese Patent Laid-Open Publication No. Hei5-341005 discloses a fault detection system that carries out fan-in tracing from the individual error observation points by testers and divides whole of the fault circuit into groups in terms of the error observation points based on information about the error observation points. In this fault detection system, a fault is assumed to perform fault simulation by an error probability calculation means. An error probability is calculated from the number of times when the individual error observation points of the particular circuit group in which this assumed fault exists have observed as error using the testers and also from the number of times when the fault detection has been made at the error observation points in the fault simulation. The result of this calculation is outputted as an error cause.
Regarding the conventional fault analysis using the EB tester, since the EB tester itself requires a special mechanism which is usually expensive, it is not suitable for use in a fault analysis of a great number of LSIs. Further, an EB tester cannot identify faults located in a deeper layer in a multi-layer structure.
Yet in a further conventional fault analysis by a multilayer-structure fault simulation on a computer, it usually takes a huge amount of computing time to locate the fault position, so this conventional analysis can hardly be applied to all types of LSIs. Another problem with this conventional analysis is that the object of analyzing is limited to the so-called stuck-at fault in which the fault mode would be fixed in some logical value.